The present invention relates to an associative memory device and, more specifically, to an associative memory device in which the precharge potential of the data lines and the inverted data lines is set to a potential between a supply potential and a ground potential.
An associative memory device is called also a content addressable memory, and comprises a plurality of associative memory cells. Each associative memory cell comprises a data storage unit to store data like an ordinary semiconductor memory does, and a data retrieval unit to retrieve data from the data storage unit. Data to be retrieved having a predetermined number of bits are stored in the data storage units of the associative memory cells. Then, the data stored in the data storage units (hereinafter referred to as "stored data") are match-retrieved with the data for match-retrieving (hereinafter referred to as "retrieval data") by the data retrieval units, that is, whether or not there are stored data matching the retrieval data and match addresses in which the matched data are stored are retrieved and outputted in a single cycle. The associative memory device capable of instantly retrieving desired data from among enormous data is used for improving the performance of a system that executes a data retrieval process frequently.
FIG. 11 shows the circuit configuration of one of the prior art associative memory cells of such an associative memory device by way of example. The associative memory cell 150 comprises a data storage unit 152 and a data retrieval unit 154.
The data storage unit 152 is an ordinary SRAM cell capable of storing 1-bit data, comprising inverters 154a and 154b, and transfer gates 156a and 156b. The respective inputs and the outputs of the inverters 154a and 154b are cross-coupled to form a latch circuit capable storing 1-bit data. One of the inputs and one of the outputs (the sources or the drains) of the transfer gates 156a and 156b are connected to the inputs of the inverters 154a and 154b (or the outputs of the inverters 154b and 154a) and the other input and the other output of the transfer gates 156a and 156b are connected to a data line DL and to an inverted data line DL, respectively, and the gates of the transfer gates 156a and 156b are connected to a common word line WL. Various kinds memory cells such as DRAM cell and ROM cell may be employed for the data storage unit instead of the SRAM cell.
The data retrieval unit 154 is an exclusive OR circuit that compares each bit of the stored data with each bit of the retrieval data. The data retrieval unit 154 comprises N-type MOS transistors (hereinafter referred to as "NMOSs") 158a, 158b, 160a and 160b. The sources of NMOSs 158a and 158b are connected to the drains of the NMOSs 160a and 160b in series respectively. The respective drains of the NMOSs 158a and 158b are connected to a common match line ML, the sources of the NMOSs 160a and 160b are connected to a common discharge line SL. The respective gates of the NMOSs 158a and 158b are connected to the respective outputs of the inverters 154a and 154b of the data storage unit, respectively, and the respective gates of the NMOSs 160a and 160b are connected to the data line DL and the inverted data line DL, respectively. The data retrieval unit 154 shown in FIG. 11 is an example only, and various types of such circuits are proposed currently.
The match line ML described above is a signal line on which the result of match retrieval between the stored data and the retrieval data outputted. A P-type MOS transistor (hereinafter referred to as "PMOS") 162 and an inverter 164 are connected to the match line ML. The drain of the PMOS 162 is connected to the match line ML, the source of the PMOS 162 is connected to a power supply, and the gate of the PMOS 162 is connected to a control line .PHI..sub.PM. The input and the output of the inverter 164 are connected to the match line ML and an encoder (not shown), respectively. The discharge line SL is a signal line through which the charge of the precharged match line ML is discharged when the stored data does not match the retrieval data. The discharged line SL is connected to a drain of NMOS 166 and a source and a gate of NMOS 166 are connected to a ground and the control line .PHI..sub.PM, respectively. A predetermined number of the associative memory cells, for example, thirty-two cells, are arranged in a row to form a word memory. Each cell in a word memory stores and compares each bit of data. All the cells in the word memory share a word line WL, the match line ML, and the discharge line SL. A predetermined number of the word memories are arranged in a column to form a memory array. That is, the associative memory cells are arranged in rows and columns. Each cell in the memory array is specified with the position of the row (row address) and the position of the column (column address). All the cells in a column share a pair of a data line and an inverted data line.
When SRAM cells are used as the storage units of the associative memory cells, both the pair of the data line and the inverted data line are connected to all of the memory cells arranged in the corresponding column.
A standby mode, a read mode for a data read operation, a write mode for a write operation and a retrieval mode for a data retrieval operation of the associative memory device comprising such associative memory cells will be described below.
In the standby mode, none of the data read operation, the data write operation and the data retrieval operation are carried out, and the word line WL and the control line .PHI..sub.pm are in LOW logical level. In this state, the pair of the data line DL and the inverted data line DL are precharged at a supply potential, i.e., a potential of the power supply, by a precharging circuit (not shown) to enhance operating speed, and the match line ML is precharged at a supply potential through the PMOS 162 to enhance retrieving speed.
In the read mode, the address of a word memory from which data are to be read is inputted to request the data read operation. When the data read operation is started, the precharging of the data line DL and the inverted data line DL at the supply potential is ended, the address is decoded and the word line WL of a selected word memory is raised to HIGH logic level. In the word memory connected to the raised word line WL, the transfer gates 156a and 156b turn ON, and then the data and its inverted data stored in the word memory are outputted through the transfer gates 156a and 156b on the data line DL and the inverted data line DL, respectively. A differential voltage signal corresponding to each bit of the data stored in the word memory is applied to the data line DL and the inverted data line DL precharged at the supply potential, and the differential voltage signal is amplified by a sense amplifier, not shown, to read the data from the selected word memory.
In the write mode, the address of a word memory to which data are to be written is inputted to request the data write operation.
When the data write operation is started, the precharging of the data line DL and the inverted data line DL at the supply potential is ended, each bit of the data and each bit of its inverted data are driven on the data line DL and the inverted data line DL by a data line driver, not shown, the address is decoded and the word line WL of a selected word memory is raised to HIGH. In the word memory connected to the raised word line WL, the transfer gates 156a and 156b turn ON, and then the data and its inverted data driven on the data line DL and the inverted data line DL are transferred through the transfer gates 156a and 156b to the inputs of the inverters 154a and 154b and are latched to write the data to the selected word memory.
In the retrieval mode for retrieving the stored data and the retrieval data is started when the data retrieval operation is requested after entering the retrieval data. When the data retrieval operation is started, the precharging of the data line DL and the inverted data line DL at the supply voltage potential is ended, each bit of retrieval data and each bit of its inverted data are driven on the data line DL and the inverted data line DL by the data line driver, not shown, the control line .PHI..sub.PM goes HIGH, the precharging of the match line ML is ended and the NMOS 166 turns ON, so that each cell in the word memory starts to compare each bit of the stored data and corresponding bit of the retrieval data. The retrieval operation starts simultaneously in all the cells in all the word memories for matching between the stored data and the retrieval data.
For example, when a logic HIGH is held as stored data, i.e., when the respective potentials of the outputs of the inverters 154b and 154a are HIGH and LOW, respectively, a HIGH is given as the retrieval data, i.e., when the respective potentials of the data line DL and the inverted data line DL are HIGH and LOW, respectively, the NMOSs 158b and 160a are ON and the NMOSs 158a and 160b are OFF. Therefore, both the series circuit of the NMOSs 158a and 160a and the series circuit of the NMOSs 158b and 160b are nonconductive, the match line ML remains in a precharged potential, i.e., HIGH logic level. Accordingly, if the stored data matches the retrieval data, the potential of the match line ML remains HIGH.
When a LOW is given as the retrieval, i.e., when the respective potentials of the data line DL and the inverted data line DL are LOW and HIGH, respectively, the series circuit of the NMOSs 158a and 160a is OFF, and the series circuit of the NMOSs 158b and 160b is ON. Consequently, the charge on the precharged match line ML is discharged through the NMOSs 158b and 160b, the discharge line SL and the NMOS 166 to the ground, and the match line ML goes LOW. Accordingly, when anyone bit of the stored data and the corresponding bit of the retrieval data are not the same, the match line ML is discharged and goes LOW.
Thus, only when every bits of the stored data stored in the associative memory cells connected to the same match line ML, for example, the associative memory cells forming a word memory and every corresponding bits of the retrieval data are the same, the match line ML is kept HIGH. And the outputs are given to an encoder, not shown, the addresses are encoded and the encoded addresses are outputted sequentially in predetermined order of priority.
This conventional associative memory device is in the standby mode before any one of the read mode, the write mode and the retrieval mode. In the standby mode, the data line DL and the inverted data line DL are precharged at the supply potential. Therefore, the potentials of the data line DL and the inverted data line DL, in general, swing between the supply potential and the ground potential during the read mode, the write mode and the retrieval mode. During these large swing of the potential, a high current flows and a large current (power) is consumed.
The data retrieval operation is not dependent on the type of the memory cells, although the detail of the data read and write operation varies with type of the used memory cells.
It was proposed to divide a memory device in two or more blocks each includes a memory array to reduce power consumption due to the swings of the potentials of the data lines and the inverted data lines. Only one of the blocks of the memory device including the selected word memory proceeds the data read or data write operation, and the other blocks are kept in the standby mode. The power consumption of a memory device, such as a SRAM or a ROM, for the data read operation and the data write operation is effectively reduced by this technique.
Since data only stored in DRAM cells are destructed when the data are read from selected cells, the read data are amplified to the full logic level (for example, the ground potential and the supply potential) by sense amplifiers and the amplified data are rewritten to the cells through the data lines connected to the selected cells. At the same time, data in all the DRAM cells which share a word line with the selected cells are also amplified and rewritten in the cells through the data lines. Similar rewriting are also made to the DRAM cells which share a word line with the selected cells during the data write operation.
However, since the DRAM stores data only temporarily in storage capacitors, the stored data is destructed in a certain time period by leakage currents at the junctions or the field isolator. Therefore, the data must be rewritten periodically to the memory cells. Such a periodical rewriting operation is called refreshing. Generally, refreshing is carried out 256 cycles per 4 ms for a 256-Kb DRAM and 512 cycles per 8.2 ms for 1-Mb DRAM; that is, all the memory cells of a 256-Kb DRAM are refreshed by 256 refreshing cycles, 4 ms.
The number of data lines and the inverted data lines which swing to the full logic level during the data read operation or the data write operation is usually determined to properly make the refresh operation. Therefore, the power consumption due to the swing of the potentials of the data lines and the inverted data lines is not effectively reduced in DRAMS by dividing into the blocks. To overcome this DRAMs by dividing into the blocks. To overcome this problem, a technique of precharging the data lines and the inverted data lines at a potential equal to half the supply potential was proposed.
However, though this technique is effective to reduce power consumption of DRAMS which need rewriting and refreshing operations, it is not employed in SRAMs and ROMs which do not need rewriting or refreshing operation.
Note that, in a DRAM with the open data line architecture, each memory array is divided in two sub arrays and the precharging circuits, the data line drivers and the sense amplifiers are arranged between the two sub arrays. Each of the each pair of the data line and the inverted data line is connected to the memory cells arranged in the corresponding column in respective sub array and to the respective dummy cell arranged adjacent to the same sub array. While, in a DRAM with the folded data line architecture, each of the each pair of the data line and the inverted data line is connected to a half of the memory cells arranged in the corresponding column in the memory array and to the respective dummy cell arranged adjacent to the memory array. That is, only one of the pair of the data line and the inverted line is connected to each of the memory cells in the corresponding column, in both cases. Each of the pair of the data line and the inverted data line is used as the data line for the memory cells to which it is connected and as the inverted data line for the cells to which the other one of the pair is connected.
However, the potentials of the data line and the inverted line in a DRAM swing to the full logic level during the data write and the data read operations as in the case in a SRAM. During the data read operation, for example, a differential voltage signal made by the difference of the charges stored in a selected cell connected to a data line and that in the dummy cell connected to the corresponding inverted data line is amplified by a sense amplifier to the full logic level.
When DRAM cells are used as the storage units of the associative memory cells, similar data line structure can be used in the associative memory device.
In the associative memory device, a word memory storing the stored data matching the retrieval data cannot generally be presupposed when carrying out the data retrieval operation. Therefore, all the data lines DL and all the inverted data lines DL corresponding to the retrieval data must be driven. If the potentials of all the data lines DL and all the inverted data lines DL swing between the ground potential and the supply potential, which is carried out by the conventional associative memory device, a high current flows and a large power is consumpted in the associative memory device. Furthermore, in the conventional associative memory device, the NMOSs 160a and 160b of the retrieval unit 154, in addition to the transfer gates 156a and 156b of the storage unit 152, are connected to the data line DL and the inverted data line DL as shown in FIG. 11 and the electrostatic capacitiances of the data line DL and the inverted data line DL of the associative memory device is greater than those of the ordinary semiconductor memory such as a SRAM and a DRAM. Therefore, the power consumption of the conventional associative memory device is very large. Such a problem in power consumption becomes more conspicuous and serious in associative memory devises as the storage capacity increases, for example, from 64 Kb to 256 Kb.